Advanced IC Packaging Solutions and Reliability Challenges 🗓

Also advanced interconnects, failure modes, chip to package interactions.

Newbury Park Map

Meeting Date: July 24, 2018
Time: 6:30 PM Networking & Food; 7:00 PM Presentation
Speaker: Dr. Richard Rao of Microsemi Corp.
Location: Newbury Park
Cost: none
RSVP: requested, through website
Event Details: IEEE vTools
Summary: This talk provides an introduction of most advanced IC packaging solutions and related reliability challenges. It covers 3D/2.5D/2.1D and FanOut WLP packaging integration, advanced interconnects such as TSV (Through Si Via) /uBumps, Si Interposer, Cu Pillar and Cu/Cu direct bonding related failure modes, and finally the Chip to Package Interaction (CPI) issues on 16 nm and beyond FinFET nodes.

Bio: Dr. Richard Rao is currently a Technical Fellow of Microsemi, a Microchip Company, a leading supplier of high reliability integrated circuits, located in Southern California and a Senior Member of IEEE. He is the present Chair of IEEE EPS (Electronics Packaging Society) Reliability Technical Committee. Dr. Rao is responsible for the corporate reliability and advanced packaging solutions. His focus is to find advanced packages to meet the high performance, high reliability and high-power semiconductor ICs; to study the new failure modes and mechanisms of cutting edge silicon and packaging technologies as well as to develop design for reliability solutions for advanced circuits, packaging and chip to package interaction. He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China. Prior to joining Vitesse Semiconductor Corp (now Microsemi) in 2004, Dr. Rao held various academic and technical positions in reliability physics and engineering. He was an associate professor at University of Science and Technology of China, a research fellow at Northwestern University, a National Science and Technology Board Research Fellow in Singapore; and a principal engineer at Ericsson Inc. He has published over 30 papers on reliability physics and applications and he is a main contributor of several JEDEC standards. He is a technical committee member of IRPS (International Reliability and Physics Symposium) and ECTC (Electronics Component and Technology Conference). He is a frequent speaker to IRPS, ECTC, ISQED (International Symposium on Quality Electronics Design), ASME Symposiums and a keynote speaker to ICEPT and International Conf on System on Chip, etc. Dr. Rao has over 20 years hands on experience and knowledge in silicon to package to system integration such as HKMG and FinFET, high performance FCBGA/CSP, WLP, 2.5D/3D, chip to package to board interaction, board and system level reliability physics and applications. He was invited to give keynote speech and tutorials on several international conferences.