Principles of Power Integrity for PDN Design 🗓

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IEE San Diego Section
Meeting Date: November 6, 2019
Time: 6:00 PM Networking & Food; 6:30 PM Presentation
Speaker: Larry D. Smith, Principal Signal Integrity engineer at Micron
Location: San Diego
Cost: none
RSVP: requested, through website
Event Details: IEEE vTools

The PDN delivers power to the on-die CMOS circuits. CMOS circuits are sensitive to the power supply voltage because of Fmax, Vmin and Jitter considerations. Logic core speed is limited by the instantaneous power supply voltage including PDN voltage droops. The power supply voltage is often raised up to overcome PDN voltage droops to enable the on-die circuit voltage to stay above the minimum voltage (Vmin) where the circuits will run at rated clock speed (a high percentage of Fmax). These are the important PDN considerations for all CMOS circuits.

Larry D. Smith Larry D. Smith is a Principal Signal Integrity engineer at Micron specializing in Power Integrity since August 2018. Prior to joining Micron, he was a PI engineer at Qualcomm in the mobile computing space beginning in 2011. He worked at Altera from 2005 to 2011 and Sun Microsystems from 1996 to 2005, where he did development work in the field of signal and power integrity. Before this, he worked at IBM in the areas of reliability, characterization, failure analysis, power supply and analog circuit design, packaging, and signal integrity. Mr. Smith received the BSEE degree from Rose-Hulman Institute of Technology and the MS degree in material science from the University of Vermont. He has more than a dozen patents and has authored numerous journal and conference papers. His most recent work is a book entitled “Principles of Power Integrity for PDN Design” published by Prentice Hall in 2017.