Heterogeneous Integration Roadmap: Interconnects for 2D and 3D Architectures 🗓

— definitions, evolution, key metrics, bandwidth, power delivery, signaling …

Webinar
On the internet Map

SCV Electron Devices, Electronics Packaging, and Photonics Chapter

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Date: Wednesday, May 13, 2019 (second in a series)
Time: 8:00 – 9:00 AM (PDT)
Speaker: Dr. Ravi Mahajan, Intel Fellow (and chair of the 2D/3D Architectures Working Group)

Cost: none

Location: on the Internet
Event Details & Registration: ieee.org

Summary:
With increasing interest in on-package integration, there is a need to describe package architectures and their interconnect capabilities in a simple and consistent manner. We will define a new standardized nomenclature covering both 2D and 3D constructions, and also key metrics. Also: support for increasing on-package bandwidth requirements; efficient power delivery; and low-loss high-speed signaling.